1. Field of the Invention
The present invention generally relates to a method of operating and a memory array of Dynamic Random Access Memory (DRAM) cells. More particularly, it relates to improving the sensing of a high data state in the DRAM cell.
2. Description of the Related Art
In various systems applications, SRAMs (Static Random Access Memories), which operate faster than DRAMs, have been employed as routers, hubs or cache memories for CPUs (Central Processing Units). However, the development of highly efficient and multifunctional information and communication systems, mandate an increase in memory capacity. The lower cost per bit of DRAM leads to a more cost efficient storage solution than SRAM. By implementing system storage with DRAM, overall bandwidth can be improved for a wide I/O (input/output) data path or a multibank memory. However, compared with SRAMs, DRAMs are remarkably slower in respect to read/write access. Consequently, the use of DRAMs is performance limited.
In the operation of DRAM (Dynamic Random Access Memory) devices, it is required to maintain data stored in a charge storage cell of an array for a maximum retention period without performing a refresh operation in order to offer high availability and low power consumption. When competing with Static RAM (SRAM) devices, it is also desirable to offer high performance with the same DRAM design.
In the current state of the art there are DRAM designs that offer either high retention times for the stored data or high performance.
A conventional DRAM sensing scheme is known as half-VDD sensing, in which both the true and complementary bit-lines are pre-charged to a value approximately halfway between a logic 1 voltage (VDD) and a logic 0 voltage (ground, or GND). When a cell is coupled to a pre-charged bit-line, the voltage will then slightly increase or decrease, depending on the value of the bit stored in the cell, thus creating a differential voltage with respect to the complementary bit-line and VDD/2.
However, for performance reasons, a ground sensing scheme pre-charges the bit-line pair to ground prior to a read operation. Because of the pre-charging to ground, reference word lines are needed to place a reference voltage (e.g., (Vread1−Vread0)/2) on either the bit-line or the complementary bit-line in order to be able to read a 0 bit.
Conventional DRAMs use sensing schemes that require amplifiers capable of sensing small sense signals. One way to amplify small sense signals has been shown to be a cross-couple sense amplifier, as is well known in the art. These cross-couple sense amplifiers require balanced true and complement bit-lines to perform and operate reliably.
In conventional DRAMs, the sense signal from a memory cell is generated by charge sharing the charge stored in the memory cell with a pre-charged bit-line, and then comparing the developed sense signal on the pre-charged bit-line to a reference bit-line.
U.S. Pat. No. 7,342,839 to Barth, Jr. is incorporated herein by reference. This reference demonstrates that 4T and 6T and Cross Coupled DRAMs require a strong Write 1, a high VPP is required to overcome Array Device Vt sigma, and 4T and 6T leakage issues at High VDD/High Temp manifests as Read 0's margin. Additionally, cross couple small signal is sensitive to noise, wherein a device mismatch mitigated by Body Tied Sense Pair, a line-to-line couple requires Bit-Line Twisting, and GND Pre-Charge Requires a Reference Cell that is susceptible to VREF Noise.
Consequently, there is a need for a direct sense system to minimize sub-Vt leakage in an SOI technology thereby improving the sensing of a high data state in a DRAM cell.